Digi NS9750 - Manual (Page 26)

N S 9 7 5 0 F e a t u r e s
2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
NS9750 Features
The NS9750 uses an ARM926EJ-S core as its CPU, with MMU, DSP extensions, Jazelle
Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard
architecture. The NS9750 runs up to 200 MHz, with a 100 MHz system and memory bus
and 50 MHz peripheral bus. The NS9750 offers an extensive set of I/O interfaces and
Ethernet high-speed performance and processing capacity. The NS9750 is designed
specifically for use in high-performance intelligent networked devices and Internet
appliances including high-performance, low-latency remote I/O, intelligent
networked information displays, and streaming and surveillance cameras.
32-bit ARM926EJ-S RISC processor
125 to 200 MHz
5-stage pipeline with interlocking
Harvard architecture
8 kB instruction cache and 4 kB data cache
32-bit ARM and 16-bit Thumb instruction sets. Can be mixed for
performance/code density tradeoffs.
MMU to support virtual memory-based OSs, such as Linux, VxWorks, others
DSP instruction extensions, improved divide, single cycle MAC
ARM Jazelle, 1200CM (coffee marks) Java accelerator
EmbeddedICE-RT debug unit
JTAG boundary scan, BSDL support
External system bus interface
32-bit data, 32-bit internal address bus, 28-bit external address bus
Glueless interface to SDRAM, SRAM, EEPROM, buffered DIMM, Flash
4 static and 4 dynamic memory chip selects
1-32 wait states per chip select
A shared Static Extended Wait register allows transfers to have up to 16368
wait states that can be externally terminated
Self-refresh during system sleep mode
Automatic dynamic bus sizing to 8 bits, 16 bits, 32 bits