Digi NS9750 User Manual
Page 793
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U S B C o n t r o l l e r M o d u l e
FIFO Interrupt Status registers
The FIFO Interrupt Status registers contain interrupt status information for the device
block FIFOs. All status bits are active high (1) and all interrupts are cleared by writing
a 1 to the appropriate field.
Note:
For diagnostic purposes, each of the interrupt status bits can be set by
writing a 1 when the bits are at 0.
All FIFO status bits operate in a catch and hold mode, which means that once a status
bit is set, it can be cleared only by writing a 1 to the corresponding bit position. If the
status generating condition is present after writing a 1, the appropriate status bit is
reasserted immediately.
Note:
The NS9750 FIFO Interrupt Status registers pertain to DMA mode only;
direct, or processor-controlled, mode is not supported at this time. The
following control signals are considered “don’t care” signals, as they are
valid only in direct mode:
FULL
,
EMPTY
,
HALF
,
OFLOW
, and
UFLOW
.
6
6
4
7
7
5
8
8
6
9
9
7
10
10
8
11
11
9
12
12
10
13
13
11
DMA channel
FIFO
EP number
Table 448: FIFO to DMA channel to endpoint map