Digi NS9750 - Manual (Page 673)

w w w . d i g i e m b e d d e d . c o m 6 4 9
S e r i a l C o n t r o l M o d u l e : S P I
When reading from the receive FIFO, the processor must perform a long word read
operation. Each time a read cycle to the receive FIFO is performed, the receive FIFO
advances to the next long word entry. The processor cannot read individual bytes
from the same FIFO long word entry.
Processor interrupts vs. DMA
The receive FIFO can be emptied using processor interrupts or the DMA controller.
Using processor interrupts
The processor can read one long word (4 bytes) of data from the receive FIFO when
the RRDY field (in "Serial Channel B/A/C/D Status Register A" on page 657) is set
active high. The long word read may have 1, 2, 3, or 4 bytes of valid data within the
word. The number of valid bytes is determined by the bit encoding in the RXFDB field
in Serial Channel B/A/C/D Status Register A. The RXFDB field must be read before the
FIFO Data register is read.
The RBC bit in Serial Channel B/A/C/D Status Register A indicates that a receive data
buffer has been closed and receiver status can be read from this register. Before
additional data can be read from the FIFO, the RBC bit must be acknowledged by
writing a 1 to the same bit position in Serial Channel B/A/C/D Status Register A.
These steps provide the recommended process flow for the serial port receiver
interrupt service routine:
1
Read Serial Channel B/A/C/D Status Register A.
2
If RRDY is true:
a
Read the data FIFO.
b
Use the RXFDB field to pick out valid bytes.
3
If RBC is true:
a
Record receiver buffer closed status (if you want to).
b
Write a 1 to the RBC bit position in Serial Channel B/A/C/D Status
register A.
c
Read Serial Channel B/A/C/D Status Register A again.
To facilitate an interrupt when either the RRDY or RBC status bits are active, the
processor must set one or both of the corresponding interrupt enables in Serial
Channel B/A/C/D Control Register A.