Ethernet general status register, Ethernet transmit status register, Register bit assignment – Digi NS9750 User Manual
Page 368: Table 208: ethernet general status register
E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 4 4
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Ethernet General Status register
Address: A060 0008
Register bit assignment
Ethernet Transmit Status register
Address: A060 0018
The Ethernet Status register contains the status for the last transmit frame. The
TXDONE bit in the Ethernet Interrupt Status register (see page 385) is set upon
completion of a transmit frame and the Ethernet Transmit Status register is loaded at
the same time. Bits [15:0] are also loaded into the Status field of the last transmit
buffer descriptor for the frame.
Bits
Access
Mnemonic
Reset
Description
D31:21
N/A
Reserved
N/A
N/A
D20
R/C
RXINIT
0x0
RX initialization complete
Set when the
RX_RD
logic has completed the
initialization of the local buffer descriptor registers
requested when ERXINIT in Ethernet General
Control Register #1 (see page 339) is set. The delay
from ERXINIT set to RXINIT set is less than five
microseconds.
D19:00
N/A
Reserved
N/A
N/A
Table 208: Ethernet General Status register
Reserved
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
RX
INIT
Reserved