Digi NS9750 - Manual (Page 143)

w w w . d i g i e m b e d d e d . c o m 1 1 9
M e m o r y C o n t r o l l e r
Chip select 1 memory configuration
You can configure the memory width and chip select polarity of static memory chip
select 1 by using selected input signals. This allows you to boot from chip select 1.
These are the bootstrap signals:
boot_strap[4:3]:
Memory width select
gpio[49]:
Chip select polarity
boot_strap[0]: Byte lane enable_n/write_enable_n
for byte-wide devices
Example: Boot from flash, SRAM mapped after boot
The system is set up as:
Chip select 1 is connected to the boot flash device.
Chip select 0 is connected to the SRAM to be remapped to
0x00000000
after
boot.
The boot sequence is as follows:
1
At power-on, the reset chip select 1 is mirrored into chip select 0 (and chip
select 4). The following signals are configured so the nonvolatile memory device
can be accessed:
– boot_strap[4:3]
– gpio[49]
2
When the power-on reset (
reset_n
) and AHB reset (
HRESETn
) go inactive, the
processor starts booting from
0x00000000
in memory.
3
The software programs the optimum delay values in the flash memory so the
boot code can run at full speed.
4
The code branches to chip select 1 so the code can continue executing from the
non-remapped memory location.
5
The appropriate values are programmed into the memory controller to configure
chip select 0.
6
The address mirroring is disabled by clearing the address mirror (M) field in the
Control register (see page 205).
7
The ARM reset and interrupt vectors are copied from flash memory to SRAM that
can then be accessed at address
0x00000000.