Fifo status register – Digi NS9750 User Manual
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B B u s s l a v e a n d D M A i n t e r f a c e
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N S 9 7 5 0 H a r d w a r e R e f e r e n c e
FIFO Status register
Address: 9040 0008
The FIFO Status register allows the CPU to determine that status of all FIFOs in the
1284 module. You can ignore this register when running the 1284 interface in DMA
mode.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:16
N/A
Reserved
N/A
N/A
D15:14
R
FCFDR
0x0
Forward command FIFO depth remain
(FwCmdFifoDepthRemain)
00
4 bytes
01
1 byte
10
2 bytes
11
3 bytes
Determines how many bytes are valid in the current
forward command FIFO entry.
The current value in the field is not valid if the FIFO is
empty.
D13
R
FCFE
0x1
Forward command FIFO empty
(FwCmdFifoEmpty)
0
FIFO is not empty
1
FIFO is empty
D12
R
FCFA
0x1
Forward command FIFO almost empty
(FwCmdFifoAlmostEmpty)
0
FIFO has more than 1–4 bytes
1
FIFO has only one 1–4 byte entry
This field is not valid if the FIFO is empty.
Table 393: FIFO Status register
FCFE
FCFA
FCFR
FDFDR
FDFE FDFAE
FDFR
RFF
RFAF
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
FCFDR
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
RFR