Digi NS9750 - Manual (Page 72)

A b o u t t h e p r o c e s s o r
4 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
About the processor
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instructions
sets, allowing you to trade off between high performance and high code density. The
processor includes features for efficient execution of Java byte codes, providing Java
performance similar to JIT but without the associated overhead.
The ARM926EJ-S supports the ARM debug architecture, and includes logic to assist in
both hardware and software debug. The processor has a Harvard-cached architecture
and provides a complete high-performance processor subsystem, including:
ARM926EJ-S integer core
Memory Management Unit (MMU) (see "Memory Management Unit (MMU),"
beginning on page 78, for information)
Separate instruction and data AMBA AHB bus interfaces