Digi NS9750 - Manual (Page 99)

w w w . d i g i e m b e d d e d . c o m 7 5
W o r k i n g w i t h t h e C P U
R13: Process ID register
The Process ID register accesses the process identifier registers. The register
accessed depends on the value on the
opcode_2
field:
Use the Process ID register to determine the process that is currently running. The
process identifier is set to 0 at reset.
FCSE PID register
Addresses issued by the ARM926EJ-S core, in the range 0 to 32 MB, are translated
according to the value contained in the FCSE PID register. Address A becomes
A + (FCSE PID x 32 MB)
; it is this modified address that the MMU and caches see.
Addresses above 32 MB are not modified. The FCSE PID is a 7-bit field, which allows
128 x 32 MB processes to be mapped.
If the FCSE PID is 0, there is a flat mapping between the virtual addresses output by
the ARM926EJ-S core and the modified virtual addresses used by the caches and MMU.
The FCSE PID is set to 0 at system reset.
If the MMU is disabled, there is no FCSE address translation.
FCSE translation is not applied for addresses used for entry-based cache or TLB
maintenance operations. For these operations,
VA=MVA
.
Use these instructions to access the FCSE PID register:
opcode_2=0 Selects the Fast Context Switch Extension (FCSE) Process Identifier (PID)
register.
opcode_2=1 Selects the context ID register.
Function Data ARM instruction
Read FCSE PID FCSE PID MRC p15,0,Rd,c13,c0,0
Write FCSE PID FCSE PID MCR p15,0,Rd,c13,c0,0