Digi NS9750 - Manual (Page 148)

S t a t i c m e m o r y c o n t r o l l e r
1 2 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
"Static Memory Page Mode Read Delay 0–3 registers" on page 237
(StaticWaitPage[n])
"Static Memory Turn Round Delay 0–3 registers" on page 239
(StaticWaitTurn[n])
"Static Memory Extended Wait register" on page 224 (StaticExtendedWait)
The number of cycles in which an AMBA transfer completes is controlled by two
additional factors:
Access width
External memory width
Each bank of the memory controller has a programmable enable for the extended
wait (EW). The WAITRD wait state field in the Static Memory Read Delay register can
be programmed to select from 1–32 wait states for read memory accesses to SRAM
and ROM, or the initial read access to page mode devices. The WAITWR wait state
field in the Static Memory Write Delay register can be programmed to select from 1–
32 wait states for access to SRAM. The Static Memory Page Mode Read Delay register
can be programmed to select from 1–32 wait states for page mode accesses.
Static memory read control
There are three types of static memory read controls:
Output enable programmable delay
ROM, SRAM, and flash
Asynchronous page mode read
Output enable programmable delay
The delay between the assertion of the chip select and the output enable is
programmable from 0 to 15 cycles using the wait output enable bits (WAITOEN) in the
Static Memory Output Enable Delay registers (see "Static Memory Output Enable Delay
0–3 registers" on page 235). The delay is used to reduce power consumption for
memories that cannot provide valid output data immediately after the chip select has
been asserted. The output enable is always deasserted at the same time as the chip
select. at the end of the transfer.