Digi NS9750 - Manual (Page 344)

E t h e r n e t M A C
3 2 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
External IO MII RMII
RXD[3] RXD[3] N/C
Pull low external to NS9750
RXD[2] RXD[2] N/C
Pull low external to NS9750
RXD[1] RXD[1] RXD[1]
RXD[0] RXD[0] RXD[0]
RX_DV RX_DV N/C
Pull low external to NS9750
RX_ER RX_ER RX_ER
Optional signal; pull low external to NS9750 if not being
used
RX_CLK RX_CLK REF_CLK
TXD[3] TXD[3] N/C
TXD[2] TXD[2] N/C
TXD[1] TXD[1] TXD[1]
TXD[0] TXD[0] TXD[0]
TX_EN TX_EN TX_EN
TX_ER TX_ER N/C
TX_CLK TX_CLK N/C
Pull low external to NS9750
CRS CRS CRS_DV
COL COL N/C
Pull low external to NS9750
MDC MDC MDC
MDIO MDIO MDIO
Table 202: PHY interface mappings to external IO