Digi NS9750 - Manual (Page 894)

I n d e x - 24
timing controller, LCD 574
TLB structure
104
transaction ordering, AHB-to-PCI
bridge 410
transferring a frame to system memory,
Ethernet
325
translation faults
101
Translation Lookaside Buffer (TLB) 78
transmission error handling, USB 714
transmit broadcast packet counter 374
transmit buffer descriptor format
Ethernet
327
Transmit Buffer Descriptor Pointer Offset
register 394
transmit byte counter 374
transmit deferral packet counter 374
transmit excessive collision packet
counter 375
transmit excessive deferral packet
counter 375
transmit FCS error counter 376
transmit FIFO interface
605
,
647
transmit fragment counter 377
transmit jabber frame counter 376
transmit late collision packet counter 375
transmit multicast packet counter 374
transmit multiple collision packet
counter 375
transmit oversize frame counter 376
transmit packet counter 374
transmit packet processor 324 , 327
Transmit Recover Buffer Descriptor
Pointer register 389
transmit single collision packet
counter 375
transmit statistics counters 373
transmit total collision packet
counter 376
transmit undersize frame counter 377
transmitting a frame to the Ethernet
MAC
330
TX Buffer Descriptor Pointer register 389
TX buffer descriptor RAM 396
TX Error Buffer Descriptor Pointer
register
390
typical power dissipation
789
U
UART
features 4
UART mode 604
See also serial controller, UART.
UNDEFINED (CP15 registers)
53
UNPREDICTABLE (CP15 registers) 52
up/down counters 263
upper and lower panel formatters 574
upstream port (USB) 708
upstream transactions
405
USB clock
15
USB Configuration register 538
USB controller 707 - 783
about 708
DC electrical inputs 790
DC electrical outputs
791
device block 710 - 712
device block architecture 710
Device Control and Status register 718
device endpoint 714
device endpoint status
770
Device IP Programming Control/Status
register 724
FIFO Interrupt Enable 0 register 776
FIFO Interrupt Enable 1 register 777
FIFO Interrupt Enable 2 register
778
FIFO Interrupt Enable 3 register
779
FIFO Interrupt Enable registers 776 -