Digi NS9750 - Manual (Page 291)

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S y s t e m C o n t r o l M o d u l e
Interrupt controller
The interrupt system is a simple two-tier priority scheme. Two lines access the CPU
core and can interrupt the processor: IRQ (normal interrupt) and FIQ (fast interrupt).
FIQ has a higher priority than IRQ.
FIQ interrupts
Most sources of interrupts on NS9750 are from the IRQ line. There is only one FIQ
source for timing-critical applications. The FIQ interrupt generally is reserved for
timing-critical applications for these reasons:
The interrupt service routine is executed directly without determining the
source of the interrupt.
Interrupt latency is reduced. The banked registers available for FIQ
interrupts are more efficient because a context save is not required.
Note:
The interrupt source assigned to the FIQ must be assigned to the highest
priority, which is 0.
IRQ interrupts
IRQ interrupts come from several different sources in NS9750, and are managed using
the Interrupt Config registers (see "Int (Interrupt) Config (Configuration) registers (0–
31)" on page 286). IRQ interrupts can be enabled or disabled on a per-level basis using
the Interrupt Enable registers. These registers serve as masks for the different
interrupt levels. Each interrupt level has two registers:
Interrupt Configuration register. Use this register to assign the source for
each interrupt level, invert the source polarity, select IRQ or FIQ, and
enable the level.
Interrupt Vector Address register. Contains the address of the interrupt
service routine.
Figure 61 illustrates a 32-vector interrupt controller.