Digi NS9750 User Manual
Page 190
Advertising
D y n a m i c m e m o r y c o n t r o l l e r
1 6 6
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Table 93 shows the outputs from the memory controller and the corresponding inputs
to the 64M SDRAM (2Mx32, pins 13 and 14 used as bank selects).
3
3
15
5
2
2
14
4
1
1
13
3
0
0
12
2
Output address
(
ADDROUT
)
Memory device
connections
AHB address to row
address
AHB address to
column address
14
BA1
11
11
13
BA0
10
10
12
-
-
-
11
-
-
-
10
10/AP
22
AP
9
9
21
-
8
8
20
-
7
7
19
9
6
6
18
8
5
5
17
7
4
4
16
6
3
3
15
5
2
2
14
4
1
1
13
3
0
0
12
2
Table 93: Address mapping for 64M SDRAM (2Mx32, RBC)
Output address
(
ADDROUT
)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 92: Address mapping for 16M SDRAM (2Mx8, RBC)
Advertising