Hcinterruptstatus register, Table 425: hccommandstatus register – Digi NS9750 User Manual
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U S B C o n t r o l l e r M o d u l e
HcInterruptStatus register
Address: 9010 100C
The HcInterruptStatus register provides status on various events that cause hardware
interrupts. When an event occurs, the NS9750 sets the corresponding bit in this
register. When a bit is set, a hardware interrupt is generated if the interrupt is
enabled in the HcInterruptEnable register (see "HcInterruptEnable register,"
beginning on page 735) and the MasterInterruptEnable bit (in the HcInterruptEnable
register) is set. The host controller driver can clear specific bits in this register by
writing a 1 to the bit positions to be cleared, but cannot set any of these bits.
D00
R/W
HCR
0b
HostControllerReset
Set by the host controller driver to initiate a software reset
of the host controller. Regardless of the functional state of
the host controller, it moves to
USBSUSPEND
state. This
bit is cleared by the host controller on completion of the
reset operation.
Bits
Access
Mnemonic
Reset
Description
Table 425: HcCommandStatus register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
RD
SF
WDH
SO
Rsvd
OC
Reserved
Reserved
RHSC
FNO
UE