Digi NS9750 - Manual (Page 434)

A b o u t t h e P C I - t o - A H B B r i d g e
4 1 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Bridge receives a target abort (
RTA
, see "Received target abort" on page
415)
Bridge signals a target abort (
STA
, see "Signaled target abort" on page 415)
Bridge master finds a parity error on read data or detects the target
asserting a master data parity error (
PERR#
, see "Master data parity error" on
page 415) and the parity error response bit in the PCI Command register
(see page 414) is set.
The PCI Status register (see page 415) contains the status bits for the interrupts
caused by PCI bus errors.
Use the PCI Bridge Interrupt Enable register (see page 435) to enable or disable
interrupt sources. Clearing an enable bit (setting the bit to 0) prevents the associated
interrupt status bit from asserting the external interrupt to the system.
When an AHB bus error occurs, the AHB address that caused the bus error is saved in
the AHB Address Error register (see "PCI Bridge AHB Error Address register" on page
433). Because multiple errors can occur before the software services the interrupt,
no new addresses are saved in the register until
AHBERR
(in the PCI Bridge Interrupt
Status register) is cleared.
When a PCI bus error occurs, the PCI address that caused the bus error is saved in the
PCI Address Error register ("PCI Bridge PCI Error Address register" on page 433).
Because multiple bus errors can occur before the software services the interrupt, no
new addresses are saved in the register until all error bits are cleared in the PCI
Status register.
The bridge can drive an interrupt to the PCI bus. This interrupt is driven from the
INTA2PCI
bit in the PCI Miscellaneous Support register (see page 426) in the PCI arbiter.
This interrupt is used only in systems in which NS9750 is not processing PCI interrupts,
and is set by software.
Transaction ordering
The AHB-to-PCI bridge maintains the request order in each direction. Transactions are
sent to the destination bus in the order in which they are received on the source bus.
No order is maintained between upstream and downstream transactions.