Hcfminterval register, Table 436: hcfminterval register – Digi NS9750 User Manual
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U S B C o n t r o l l e r M o d u l e
HcFmInterval register
Address: 9010 1034
The HcFmInterval register contains the 14-bit value that indicates the bit time
interval in a frame (that is, between two consecutive SOFs), and a 15-bit value
indicating the full speed maximum packet size that the host controller can transmit
or receive without causing a scheduling overrun. The host controller driver can
perform minor adjustment on the FrameInterval by writing a new value over the
present one at each SOF. This provides the programmability necessary for the host
controller to synchronize with an external clocking resource and to adjust any
unknown local clock offset.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31
R/W
FIT
0b
FrameIntervalToggle
The host controller driver toggles this bit whenever it
loads a new value to FrameInterval.
D30:16
R/W
FSMPS
0
FSLargestDataPacket
Specifies a value that is loaded into the largest data packet
counter at the beginning of each frame. The counter value
represents the largest amount of data, in bits, that can be
sent to received by the host controller in a single
transaction, at any given timer, without causing
scheduling overrun.
The field value is calculated by the host controller driver.
D15:14
N/A
Reserved
N/A
N/A
Table 436: HcFmInterval register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
FrameInterval (FI)
FSMPS
FIT