Fifo interrupt enable 2 register – Digi NS9750 User Manual
Page 802
U S B D e v i c e E n d p o i n t F I F O C o n t r o l a n d D a t a r e g i s t e r s
7 7 8
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
FIFO Interrupt Enable 2 register
Address: 9010 3024
Register bit assignment
D07
R/W
ACK3
0
Generate an interrupt when ACK3 in FIFO Interrupt
Status 1 register is asserted.
D06
R/W
NACK3
0
Generate an interrupt when NACK3 in FIFO Interrupt
Status 1 register is asserted.
D05
R/W
ERROR3
0
Generate an interrupts when ERROR3 in FIFO Interrupt
Status 1 register is asserted.
D04:00
N/A
Reserved
N/A
Not valid in DMA mode.
Bits
Access
Mnemonic
Reset
Description
D31
R/W
ACK10
0
Generate an interrupt when ACK10 in FIFO Interrupt
Status 2 register is asserted,
D30
R/W
NACK10
0
Generate an interrupt when NACK10 in FIFO Interrupt
Status 2 register is asserted.
D29
R/W
ERROR10
0
Generate an interrupt when ERROR10 in FIFO Interrupt
Status 2 register is asserted.
D28:24
N/A
Reserved
N/A
Not valid in DMA mode.
D23
R/W
ACK9
0
Generate an interrupt when ACK9 in FIFO Interrupt
Status 2 register is asserted.
D22
R/W
NACK9
0
Generate an interrupt when NACK9 in FIFO Interrupt
Status 2 register is asserted.
Table 456: FIFO Interrupt Enable 2 register
Bits
Access
Mnemonic
Reset
Description
Table 455: FIFO Interrupt Enable 1 register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
ERROR
8
Reserved
ACK8 NACK
8
Reserved
ACK7 NACK
7
ERROR
7
ACK
10
NACK
10
ERROR
10
ERROR
9
NACK
9
ACK9
Reserved