Digi NS9750 - Manual (Page 640)

S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s
6 1 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Bits Access Mnemonic Reset Description
D31:28 R/W RDM 0x0 Enable receive data match
[31] RDM1
[30] RDM2
[29] RDM3
[28] RDM4
Enables the receive data match comparators.
A receive data match comparison detection can be used to
close the current receive buffer descriptor. The last byte in
the current receive data buffer contains the match
character. Each of these bits enables the respective byte
found in the Receive Match register.
D27 R/W RBGT 0 Receive buffer GAP timer
Detects the maximum allowed time from when the first
byte is placed into the receive data buffer and when the
receive data buffer is closed.
When RBGT is set to 1, the BGAP field in Serial Channel
B/A/C/D Status Register A is set when the timeout value
defined in the Receive Buffer GAP Timer register has
expired.
D26 R/W RCGT 0 Receive character GAP timer
Detects the maximum allowed time from when the last
byte is placed into the receive data buffer and when the
data buffer is closed.
When RCGT is set to 1, the CGAP field in Serial Channel
B/A/C/D Status Register A is set when the timeout value
defined in the Receive Character GAP Timer register has
expired.
D25:22 R/W Not used 0 Must be written as 0.
D21:20 R/W MODE 00 Serial channel mode
00 UART mode
01 Reserved
10 SPI master mode
11 SPI slave mode
Configures the serial channel to operate in UART or SPI
mode. The MODE field must be set before the CE bit in
Serial Channel B/A/C/D Control Register A is set to 1.
Table 368: Serial Channel B/A/C/D Control Register B