Digi NS9750 - Manual (Page 587)

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L C D C o n t r o l l e r
Mono STN panels
Mono STN panels support one or more of these modes:
1 bpp, palettized, 2 grayscales selected from 15
2 bpp, palettized, 4 grayscales selected from 15
4 bpp, palettized, 15 grayscales selected from 15
LCD power up and power down sequence support
This procedure provides an example of how the LCD controller can be programmed to
provide the powerup sequence to an LCD panel (see Figure 85, "Power up and power
down sequences," on page 564):
1
V
DD
is applied simultaneously to the NS9750 and panel display driver logic. The
following signals are pulled up to V
DD
until the LCD controller is configured:
CLLP,
CLCP, CLFP, CLAC, CLD[23:0],
and
CLLE
.
2
After the LCD controller is configured, a 1 is written to the LcdEn bit in the
LCDControl register. This enables the
CLLP, CLCP, CLFP, CLAC,
and
CLLE
signals, but
the
CLD[23:0]
signals will be low.
3
When the signals in Step 2 have stabilized, the contrast voltage, V
EE
(which is
not controlled or supplied by the LCD controller), is applied where appropriate.
If required, a software timer routine can be used to provide the minimum
display specific delay time between application of V
DD
and application of V
EE
.
4
If required, a software timer routine can be used to provide the minimum
display specific delay time between application of the control signals and power
to the panel display. When the software timer routine completes, power is
applied to the panel by writing a 1 to the LcdPwr bit in the LcdControl register,
which, in turn, sets the
CLPOWER
signal high and enables the
CLD[23:0]
signals into
their active state. The
CLPOWER
signal gates the power to the LCD panel.
The power down sequence is the reverse of the powerup procedure, with the
respective register bits written to 0 rather than 1.