Digi NS9750 - Manual (Page 641)

w w w . d i g i e m b e d d e d . c o m 6 1 7
S e r i a l C o n t r o l M o d u l e : U A R T
Serial Channel B/A/C/D Status Register A
Address: 9020 0008 / 0048
9030 0008 / 0048
The fields in Serial Channel B/A/C/D Status Register A operate differently when DMA
mode is used. Many fields are not required for DMA mode, as they are copied to the
status field in the DMA buffer descriptor. See the discussion of the DMA Buffer
Descriptor register status field in the BBus DMA Controller chapter.
D19 R/W BITORDR 0 Bit ordering
0 Bits are processed LSB first, MSB last
1 Bits are processed MSB first, LSB last
Controls the order in which bits are transmitted and
received in the Serial Shift register.
D18:16 R/W Not used 0 Must be written as 0.
D15 R/W RTSTX 0 Enable active RTS only while transmitting
Controls the RTS indicator.
When RTSTX is set, the RTS output goes active only
when the transmitter is actively sending a transmit
character.
RTSTX allows external hardware to use the RTS signal as
a transmit line driver enable signal in multi-drop
applications.
Note: The RTS field in Serial Channel Control
Register A must also be set. If the RTSRX field
in Serial Channel Control Register A is set,
however, do not set this — the RTSTX —
field.
D14:12 R/W Not used 000 Must be written as 0.
D11:06 N/A Reserved N/A N/A
D05 R/W Not used 0 Must be written as 0.
D04:00 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 368: Serial Channel B/A/C/D Control Register B