Digi NS9750 - Manual (Page 495)

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B B u s B r i d g e
DMA accesses
There are two DMA controllers on the NS9750 BBus. One DMA controller services all
BBus peripherals except the USB device; the other is dedicated to the USB device.
Each DMA controller contains 16 channels that perform both DMA read and DMA write
transactions.
Note:
The USB host is a bus mastering BBus peripheral.
DMA memory-to-peripheral transfers (DMA read). DMA read transactions
begin with the DMA controller arbitrating for BBus control. When the bus
has been granted, the read transaction is presented to the BBus slave
interface within the BBus bridge. The command then is passed into the BBus
command retiming FIFO, where the user interface picks it up and passes it
to the AHB master interface. The AHB master arbitrates for the AHB bus,
performs the specified AHB read transaction, and returns the data to the
BBus retiming data FIFO. When the BBus slave detects the data in the
retiming data FIFO, the BBus slave can respond to the read request from the
BBus master.
The AMBA AHB bus can indicate the burst size at the beginning of a new
transfer; the AHB master sets the
hburst[2:0]
signals to the appropriate value.
Because the BBus cannot indicate burst size, the user interface always
issues a 4-transfer (4-word) request, which goes into the BBus retiming
FIFO. When data is transferred to the BBus, as many words as are needed
are moved. When the BBus read transaction completes, any words
remaining in the retiming FIFO are flushed.
DMA peripheral-to-memory transfers (DMA write). DMA write transactions
begin with the DMA controller arbitrating for control of the BBus. Once the
bus is granted, the write transaction is presented to the BBus slave
interface within the BBus bridge. The BBus slave interface passes the
command data to the BBus data retiming FIFO, but retains the command
until the BBus transaction completes. At this point, the BBus slave knows
the size of the burst (by counting the number of transfers); that information
is passed with the command to the BBus retiming command FIFO. When the
BBus detects the presence of the command, it passes the command to the
AHB master. The AHB master arbitrates for the AHB bus and performs the
AHB write transaction.