Digi NS9750 - Manual (Page 348)

E t h e r n e t f r o n t - e n d m o d u l e
3 2 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
memory. Bad frames (for example, invalid checksum or code violation) and frames
with unacceptable destination addresses are discarded.
The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the
receive byte count is analyzed. The receive byte count is analyzed by the receive
packet processor to select the optimum-sized buffer for transferring the received
frame to system memory. The processor can use one of four different-sized receive
buffers in system memory.
The transmit packet processor transfers frames constructed in system memory to the
Ethernet MAC. The software initializes a buffer descriptor table in a local RAM that
points the transmit packet processor to the various frame segments in system
memory. The 256-byte TX_FIFO decouples the data transfer to the Ethernet MAC from
the AHB bus fill rate.
Receive packet processor
As a frame is received from the Ethernet MAC, it is stored in the receive data FIFO. At
the end of the frame, an accept/reject decision is made based on several conditions.
If the packet is rejected, it is essentially flushed from the receive data FIFO.
If a frame is accepted, status signals from the MAC, including the receive size of the
frame, are stored in a separate 32-entry receive status FIFO; the
RX_RD
logic is
notified that a good frame is in the FIFO.
If the
RX_WR
logic tries to write a full receive data FIFO anytime during the frame, it
flushes the frame from the receive data FIFO and sets
RXOVFL_DATA
(RX data FIFO
overflowed) in the Ethernet Interrupt Status register. For proper operation, reset the
receive packet processor using the ERX bit in the Ethernet General Control Register
#1 when this condition occurs. If the
RX_WR
logic tries to write a full receive status
FIFO at the end of the frame, the
RX_WR
logic flushes the frame from the receive
data FIFO and sets
RXOVFL_STAT
(RX status FIFO overflowed) in the Ethernet Interrupt
Status register.
Power down mode
The
RX_WR
logic supports the NS9750’s system power down and recovery
functionality. In this mode, the RX clock to the MAC and the
RX_WR
logic are still
active, but the clock to the
RX_RD
and AHB interface is disabled. This allows frames