Pci bridge configuration register – Digi NS9750 User Manual
Page 456
P C I b u s a r b i t e r
4 3 2
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
PCI Bridge Configuration register
Address: A030 0020
The PCI Bridge Configuration register controls the bandwidth allocated to the bridge.
Change the
AHBBRST
field only during system initialization, when there is no traffic to
or from the bridge. Because the setting of this register affects NS9750’s bandwidth
allocation, changes will have an effect on system performance.
Register bit assignment
D23:16
R/W
MAX_LATENCY
0x00
Max latency value
Value to be inserted into the PCI Max_Lat
register. Defaults to
0x00
.
D15:08
R/W
MIN_GRANT
0x00
Min grant value
Value to be inserted into the PCI Min_Gnt
register. Defaults to
0x00
.
D07:00
R/W
INTERRUPT_PIN
0x01
Interrupt pin value
Value to be inserted onto the PCI Interrupt Pin
register. Defaults to
0x01
, which is the encoding
for INTA#.
Bits
Access
Mnemonic
Reset
Description
D31:02
Hardwired to
0
Reserved
N/A
N/A
Table 268: PCI Bridge Configuration register
Bits
Access
Mnemonic
Reset
Description
Table 267: PCI Configuration 3 register
Reserved
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
AHBBRST
Reserved