Digi NS9750 - Manual (Page 97)

w w w . d i g i e m b e d d e d . c o m 7 3
W o r k i n g w i t h t h e C P U
Cache unlock procedure
To unlock the locked down portion of the cache, write to Cache Lockdown register
(R9) setting
L==0
for the appropriate bit. The following sequence, for example, sets
the L bit to 0 for way 0 of the ICache, unlocking way 0:
MRC p15, 0, Rn, c9, c0, 1;
BIC Rn, Rn, 0x01 ;
MCR p15, 0, Rn, c9, c0, 1;
R10: TLB Lockdown register
The TLB Lockdown register controls where hardware page table walks place the TLB
entry — in the set associative region or the lockdown region of the TLB. If the TLB
entry is put in the lockdown region, the register indicates which entry is written. The
TLB lockdown region contains eight entries (see the discussion of the TLB structure in
"TLB structure," beginning on page 104, for more information).
Figure 21 shows the TLB lockdown format.
Figure 21: TLB Lockdown register format
When writing the TLB Lockdown register, the value in the P bit (D0) determines in
which region the TLB entry is placed:
TLB entries in the lockdown region are preserved so invalidate-TLB operations only
invalidate the unpreserved entries in the TLB; that is, those entries in the set-
associative region. Invalidate-TLB single entry operations invalidate any TLB entry
corresponding to the modified virtual address given in
Rd
, regardless of the entry’s
preserved state; that is, whether they are in lockdown or set-associative TLB regions.
P=0 Subsequent hardware page table walks place the TLNB entry in the set associative region
of the TLB.
P=1 Subsequent hardware page table walks place the TLB entry in the lockdown region at the
entry specified by the victim, in the range 0–7.
Victim SBZ/UNP
31 28 25 29 26 0
SBZ P