Digi NS9750 - Manual (Page 102)

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7 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
DSP
The ARM926EJ-S processor core provides enhanced DSP capability. Multiply
instructions are processed using a single cycle 32x16 implementation. There are
32x32, 32x16, and 16x16 multiply instructions, or Multiply Accumulate (MAC), and
the pipeline allows one multiply to start each cycle. Saturating arithmetic improves
efficiency by automatically selecting saturating behavior during execution, and is
used to set limits on signal processing calculations to minimize the effect of noise or
signal errors. All of these instructions are beneficial for algorithms that implement
the following:
GSM protocols
FFT
State space servo control
Memory Management Unit (MMU)
The MMU provides virtual memory features required by systems operating on
platforms such as WindowsCE or Linux. A single set of two-level page tables stored in
main memory control the address translation, permission checks, and memory region
attributes for both data and instruction accesses. The MMU uses a single, unified
Translation Lookaside Buffer (TLB) to cache the information held in the page tables.
TLB entries can be locked down to ensure that a memory access to a given region
never incurs the penalty of a page table walk.
MMU Features
Standard ARM926EJ-S architecture MMU mapping sizes, domains, and access
protection scheme.
Mapping sizes, as follows:
–
1 MB for sections
–
64 KB for large pages
–
4 KB for small pages
–
1 KB for tiny pages