Digi NS9750 User Manual
Page 262
R e g i s t e r s
2 3 8
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Static Memory Write Delay 0–3 registers
Address: A070 0214 / 0234 / 0254 / 0274
The Static Memory Write Delay 0–3 registers allow you to program the delay from the
chip select to the write access. These registers control the overall period for the
write cycle. It is recommended that these registers be modified during system
initialization, or when there are no current or outstanding transactions. Wait until
the memory controller is idle, then enter low-power or disabled mode.These
registers are not used if the extended wait bit is enabled in the related Static Memory
Configuration register (see page 230).
Register bit assignment
Bits
Access
Mnemonic
Description
D31:05
N/A
Reserved
N/A (do not modify)
D04:00
R/W
WTWR
Write wait states (WAITWR)
00000–11110
(n+2) HCLK cycle write access time. The wait
state time for write accesses after the first read is
WAITWR (n+2) x t
HCLK
11111
332 HCLK cycle write access time (reset value on
reset_n
)
SRAM wait state time for write accesses after the first read.
Table 164: Static Memory Write Delay 0–3 registers
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WTWR