Digi NS9750 - Manual (Page 527)

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B B u s D M A C o n t r o l l e r
Figure 83 shows the BBus DMA controller block.
Figure 83: DMA controller block
Each DMA controller arbiter determines in which channel the state machine currently
is operating.
DMA context memory
Each DMA controller maintains state for all 16 channels using an on-chip SRAM known
as the context memory. One 128x32 single port SRAM macrocell comprises this
memory. Table 302 defines the entries that describe the state of each DMA channel.
BBUS Interface
BBUS
Channel
Transfer
Attributes
DMA
Channel
Arbiter
DMA
Control
State Machine DMA
Context
RAM
128x32