Digi NS9750 - Manual (Page 622)

I n t e r r u p t s
5 9 8 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Interrupts
The LCD controller drives a single interrupt back to the system, from four interrupt
sources.
Each of the three individual maskable interrupt sources is enabled or disabled by
changing the mask bits in the LCDINTRENABLE register. The status of the individual
interrupt sources can be read from the LCDStatus register.
The interrupt sources are described next.
MBERRORINTR — Master bus error interrupt
The master bus error interrupt is asserted when an error response is received by the
master interface during a transaction with a slave. When such an error occurs, the
master interface enters an error state and remains in this state until the error is
cleared (error clearance has been signalled to the master). When the respective
interrupt service routine has completed, the master bus error interrupt can be
cleared by writing a 1 to the MBERROR bit in the LCDStatus register. This action
releases the master interface from its error state to the start of the frame state,
allowing a fresh frame of data display to be initiated.
VCOMPINTR — Vertical compare interrupt
The vertical compare interrupt is asserted when one of the four vertical display
regions, selected using the LCDControl register, is reached. The interrupt can occur
at the beginning of one of the following:
Vertical synchronization
Back porch
Active video
Front porch
This interrupt can be cleared by writing a 1 to the Vcomp bit in the LCDStatus
register.