Digi NS9750 User Manual
Page 841
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T i m i n g
Notes:
1
Minimum times are specified with 0pf and maximum times are specified with 30pf.
2
pci_clk_out
high and low times specified as 50% of the clock period +/-1 ns.
Parameter
Description
Min
Max
Units
Notes
P1
pci_clk_in to signal valid delay
2
10
ns
1
P2
Input setup to pci_clk_in
5
ns
1
P3
Input hold from pci_clk_in
0
ns
P4
pci_clk_in to signal active
2
ns
1
P5
pci_clk_in to signal float
28
ns
1
P6
pci_clk_out high time
50%-1
50%+1
ns
2
P7
pci_clk_out low time
50%-1
50%+1
ns
2
P8
pci_clk_in cycle time
30
ns
P9
pci_clk_in high time
11
ns
P10
pci_clk_in low time
11
ns
Table 472: CardBus timing characteristics
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