Digi NS9750 - Manual (Page 747)

w w w . d i g i e m b e d d e d . c o m 7 2 3
U S B C o n t r o l l e r M o d u l e
D19 R DMA6 0 DMA channel 6 interrupt. Service in the USB DMA
block.
D18 R DMA5 0 DMA channel 5 interrupt. Service in the USB DMA
block.
D17 R DMA4 0 DMA channel 4 interrupt. Service in the USB DMA
block.
D16 R DMA3 0 DMA channel 3 interrupt. Service in the USB DMA
block.
D15 R DMA2 0 DMA channel 2 interrupt. Service in the USB DMA
block.
D14 R DMA1 0 DMA channel 1 interrupt. Service in the USB DMA
block.
D13 N/A Reserved N/A N/A
D12 R FIFO 0 Bit-wise logical OR of the FIFO interrupt status fields.
D11 RW1TC URST 0 Asserted when the NS9750 is in device mode and receives
an interrupt from the host.
D10 RW1TC SOF 0 Asserted when the NS9750 is in device mode and receives
an SOF (start of frame) packet.
D09 RW1TC SUSPEND
SSPND
0 Suspend
Asserted when either the device or the host has entered the
suspend state.
D08 RW1TC SETINTF 0 Set interface
Asserted when the USB is configured for device operation
and a set interface packet is received.
D07 RW1TC SETCFG 0 Set configuration
Asserted when the USB is configured for device operation
and a set configuration packet is received.
D06 RW1TC WAKEUP 0 Wakeup
Asserted when the USB is configured for host operation
and the NS9750 moves from the suspend state to the
resume state.
D05:02 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 420: Global Interrupt Status register