Digi NS9750 - Manual (Page 343)

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E t h e r n e t C o m m u n i c a t i o n M o d u l e
Table 202 shows how the different PHY interfaces are mapped to the external IO. In
addition to these signals, NS9750 has a dedicated interrupt input for the external PHY
(
enet_phy_int
).
MIIM MII management
Provides control/status path to MII and RMII PHYs.
STAT Statistics module
Counts and saves Ethernet statistics.
SAL Station address logic
Performs destination address filtering.
MII Media Independent Interface
Provides the interface from the MAC core to a PHY that supports the MII
(as described in the IEEE 802.3 standard).
RMII Reduced Media Independent Interface
Provides the interface from the MAC core to a PHY that supports RMII.
Advisory: Note that the NS9750 RMII interface incorrectly handles
packets with dribble. (Dribble occurs when extra data is
detected on the end of a packet, but there is insufficient data
to form a new byte.)
In some cases, packets with dribble will be passed through
with the extra data truncated; this is the correct handling,
and the packet is treated as a normal packet without error.
In other cases, packets with dribble will be passed through
with an extra byte at the end. In these situations, the packet
is rejected correctly because it appears to have an invalid
FCS.
In addition, the dribble bit (RXDR) in the status field of RX
Ethernet packets and in the Ethernet Receive Status register
(see "Ethernet Receive Status register" on page 347) may
be falsely set for packets that do not have any dribble bits.
For RMII, the dribble bit should be ignored.
For RMII, ignore the Receive Alignment Error Counter and
the Receive FCS Error Counter. Set the M1RFC and
M1RAL bits in the Carry Register 1 Mask register to 1 so
no interrupts will be caused when these counters overflow.
Feature Description
Table 201: Ethernet MAC features