Digi NS9750 - Manual (Page 530)

D M A b u f f e r d e s c r i p t o r
5 0 6 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
DMA transfer status
The DMA buffer descriptor status field is updated when the buffer descriptor is
retired. Tables 304 through 309 provide a brief description of the 16-bit status fields
for each peripheral. See the appropriate chapters in this manual for more
information about each bit.
I The interrupt bit. When set, this bit tells the DMA controller to issue an
interrupt to the CPU when the buffer is closed due to a normal channel
completion. The interrupt occurs no matter what the normal completion
interrupt enable configuration is for the DMA channel.
L The last bit. This bit indicates end-of-packet status.
In fly-by peripheral-to-memory operations, this bit indicates that the buffer
was closed due to an end-of-packet status signal from the peripheral to the
DMA controller.
In fly-by memory-to-peripheral operations, this bit indicates to the DMA
controller that this buffer descriptor marks the end of the packet.
Note: For USB-IN transactions (DMA read), this bit must always be set to
1.
F The full bit. When set, this bit indicates that the buffer is full. A DMA channel
sets this bit after filling a buffer. A DMA channel clears this bit after emptying
a buffer.
A DMA channel does not try to empty a buffer with the F bit clear. Similarly, a
DMA channel does not try to fill a buffer with the F bit set.
When firmware modifies the F bit, the firmware also must write a 1 to the CE
bit in the DMA Channel Control register to activate the idle channel.
Reserved You must write a 0 to this field.
Status 16-bit status field. The USB and serial controllers use this field to store transmit
and receive status words that result from a completed transmit or receive data
frame.
Be advised: The BBus DMA buffer descriptor status field may not reflect
the occurrence of a receive overrun in the serial module.
Field Description
Table 303: DMA buffer descriptor definition