Digi NS9750 - Manual (Page 346)

E t h e r n e t M A C
3 2 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
If any of the counters roll over, an associated carry bit is set in the Carry 1 (CAR1) or
Carry 2 (CAR2) registers (see "General Statistics registers," beginning on page 377).
Any statistics counter overflow can cause the
STOVFL
bit in the Ethernet Interrupt
Status register (see page 385) to be set if its associated mask bit is not set in Carry
Mask Register 1 or Carry Mask Register 2 (see "General Statistics registers," beginning
on page 377).
The counters support a clear on read capability that is enabled when
AUTOZ
is set to 1
in the Ethernet General Control Register #2.