Digi NS9750 User Manual
Page 443
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P C I - t o - A H B B r i d g e
NS9750 can be configured to use either the embedded PCI arbiter or an external
arbiter through the bootstrap initialization scheme used during powerup (see
"Bootstrap initialization" on page 272). The
RTCK
pin selects the source of the arbiter:
The internal arbiter is used if
RTCK = 1
.
If a pulldown resistor is placed on the
RTCK
bit, an external arbiter is used.
When an external arbiter is used, the
REQ#/GNT#
(request/grant) signals for
the internal PCI-to-AHB bridge are brought to external pins on NS9750 (see
Figure 73, "System connections to NS9750 — External arbiter and central
resources," on page 457).
PCI arbiter functional description
The PCI bus arbiter supports up to four PCI masters, including the PCI-to-AHB bridge,
using the rotating priority scheme shown in Table 258. With rotating priority, the
priority of a master depends on its relative position to the last granted master. After
reset, the arbiter defaults to the PCI-to-AHB bridge having the highest priority.
Each master has a set of
REQ#/GNT#
signals used for bus arbitration. The master asserts
its
REQ#
when it needs to execute a bus transaction. The arbiter then asserts the
GNT#
to the requester with the highest priority. Until the bus is idle (that is,
FRAME#
and
IRDY#
are both inactive), the arbiter continually arbitrates and the asserted
GNT#
can
change each clock cycle. One
GNT#
can be negated coincident with another
GNT#
being asserted in this situation. When the bus goes idle, the arbiter stops arbitrating
and the master with the asserted
GNT#
is allowed to start a transaction.
Last granted
master
Highest
priority
2
nd
priority
3
rd
priority
Lowest
priority
Parked
master
PCI-to-AHB
bridge
External master
1
External master
2
External master
3
PCI-to-AHB
bridge
PCI-to-AHB
bridge
External master
1
External master
2
External master
3
PCI-to-AHB
bridge
External master
1
External master
1
External master
2
External master
3
PCI-to-AHB
bridge
External master
1
External master
2
External master
2
External master
3
PCI-to-AHB
bridge
External master
1
External master
2
External master
3
External master
3
Table 258: Rotating priority scheme