Digi NS9750 User Manual
Page 690
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S e r i a l p o r t c o n t r o l a n d s t a t u s r e g i s t e r s
6 6 6
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
the Serial Channel FIFO Data register automatically clears the RRDY bit in Serial
Channel Status Register A.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:00
R/W
DATA
0x00000000
Serial channel FIFO data field.
Table 388: Serial Channel B/A/C/D FIFO Data register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
DATA
DATA
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