Digi NS9750 User Manual
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P C I - t o - A H B B r i d g e
PCI Bridge AHB to PCI Memory Address Translate 0 register
Address: A030 0034
The PCI Bridge AHB-to-PCI Memory Address Translate 0 register translates the AHB
addresses sent to the PCI-to-AHB bridge to the appropriate PCI memory addresses.
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31
Hardwired to
0
Reserved
N/A
N/A
D30:24
R/W
PALT3VAL
0x00
Bits [31:25] of PCI address when AHB address
[27:25] = 011.
D23
Hardwired to
0
Reserved
N/A
N/A
D22:16
R/W
PALT2VAL
0x00
Bits [31:25] of PCI address when AHB address
[27:25] = 010.
D15
Hardwired to
0
Reserved
N/A
N/A
D14:08
R/W
PALT1VAL
0x00
Bits [31:25] of PCI address when AHB address
[27:25] = 001.
D07
Hardwired to
0
Reserved
N/A
N/A
D06:00
R/W
PALT0VAL
0x00
Bits [31:25] of PCI address when AHB address
[27:25] - 000.
Table 273: PCI Bridge AHB-to-PCI Memory Address Translate 0 register
Rsvd
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
PALT3VAL
Rsvd
Rsvd
Rsvd
PALT2VAL
PALT1VAL
PALT0VAL