Digi NS9750 - Manual (Page 598)

A H B i n t e r f a c e
5 7 4 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
In 16- and 24-bpp TFT mode, the palette is bypassed and the pixel serializer output is
used as the TFT panel data.
Grayscaler
A unique grayscale algorithm drives mono and color STN panels.
For mono displays, the algorithm provides 15 grayscales.
For STN color displays, the three color components (red, green, and blue)
are grayscaled simultaneously, resulting in 3375 (15 x 15 x 15) colors
available. The grayscaler transforms each 4-bit gray value into a sequence
of activity-per-pixel over several frames, relying somewhat on the display
characteristics, to give representation of grayscales and color.
Upper and lower panel formatters
Each formatter consists of three 3-bit (red, green, and blue) shift left registers. Red,
green, and blue pixel data bit values from the grayscaler are shifted concurrently
into the respective registers. When enough data is available, a byte is constructed by
multiplexing the registered data to the correct bit position to satisfy the RGB data
pattern of the LCD panel. The byte is transferred to the 3-byte FIFO, which has
enough space to store eight color pixels.
Panel clock generator
The panel clock generator block output is the panel clock. This is a divided down
version of
CLCDCLK
, and can be programmed in the range
CLCDCLK/2
to
CLCDCLK/33
to
match the bpp data rate of the LCD panel.
Timing controller
The timing controller block’s primary function is to generate the horizontal and
vertical timing panel signals. The timing controller also provides the panel bias/
enable signal. Use the AHB slave interface to program these signals in the appropriate
registers.