Digi NS9750 - Manual (Page 127)

w w w . d i g i e m b e d d e d . c o m 1 0 3
W o r k i n g w i t h t h e C P U
Nonbuffered writes
Noncached read-lock-write
(SWP)
sequence
For a read-lock-write
(SWP)
sequence, the write is always attempted if the read
externally aborts.
A swap to an NCB region is forced to have precisely the same behavior as a swap to an
NCNB region. This means that the write part of a swap to an NCB region can be
aborted externally.
Enabling the MMU
Before enabling the MMU using the R1: Control register (see page 58), you must
perform these steps:
1
Program the R2: Translation Table Base register (see page 61) and the R3:
Domain Access Control register (see page 61).
2
Program first-level and second-level page tables as required, ensuring that a
valid translation table is placed in memory at the location specified by the
Translation Table Base register.
When these steps have been performed, you can enable the MMU by setting R1:
Control register bit 0 (the M bit) to high.
Care must be taken if the translated address differs from the untranslated address,
because several instructions following the enabling of the MMU might have been
prefetched with MMU off (
VA=MVA=PA
). If this happens, enabling the MMU can be
considered as a branch with delayed execution. A similar situation occurs when the
MMU is disabled. Consider this code sequence:
MRC p15, 0, R1, c1, C0, 0 ; Read control register
ORR R1, #0x1 ; Set M bit
MCR p15, 0,R1,C1, C0,0 ; Write control register and enable MMU
Fetch Flat
Fetch Flat
Fetch Translated
Note:
Because the same register (R1: Control register) controls the enabling of
ICache, DCache, and the MMU, all three can be enabled using a single
MCR
instruction.