Digi NS9750 - Manual (Page 147)

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M e m o r y C o n t r o l l e r
Memory mapped peripherals
Some systems use external peripherals that can be accessed using the static memory
interface. Because of the way many of these peripherals function, the read and write
transfers to them must not be buffered. The buffer must therefore be disabled.
Static memory initialization
Static memory must be initialized as required after poweron reset
(reset_n)
by
programming the relevant registers in the memory controller as well as the
configuration registers in the external static memory device.
Access sequencing and memory width
The data width of each external memory bank must be configured by programming
the appropriate bank configuration register (Static Memory Configuration 0–3). When
the external memory bus is narrower that the transfer initiated from the current
main bus master, the internal bus transfer takes several external bus transfers to
complete.
For example, if bank 0 is configured as 8-bit wide memory and a 32-bit read is
initiated, the AHB bus stalls while the memory controller reads four consecutive
bytes from the memory. During these accesses, the static memory controller block
demultiplexes the four bytes into one 32-bit word on the AHB bus.
Wait state generation
Each bank of the memory controller must be configured for external transfer wait
states in read and write accesses. Configure the banks by programming the
appropriate bank control registers:
"Static Memory Configuration 0–3 registers" on page 230 (StaticConfig[n])
"Static Memory Write Enable Delay 0–3 registers" on page 234
(StaticWaitWen[n])
"Static Memory Output Enable Delay 0–3 registers" on page 235
(StaticWaitOen[n])
"Static Memory Read Delay 0–3 registers" on page 236 (StaticWaitRd[n])
"Static Memory Write Delay 0–3 registers" on page 238 (StaticWaitWr[n])