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M e m o r y C o n t r o l l e r
Dynamic Memory Data-in to Active Command Time register
Address: A070 0040
The Dynamic Memory Data-in to Active Command Time register allows you to program
the data-in to active command time, t
DAL
. It is recommended that this register be
modified during system initialization, or when there are no current or outstanding
transactions. Wait until the memory controller is idle, then enter low-power or
disabled mode. This value normally is found in SDRAM data sheets as t
DAL
or t
APW
.
Note:
The Dynamic Memory Data-in Active Command Time register is used for
all four dynamic memory chip selects. The worst case value for all chip
selects must be programmed.
Register bit assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
DAL
Data-in to active command (t
DAL
or t
APW
)
0x0–0xE
n+1 clock cycles, where the delay is in
CLK
cycles.
0xF
15 clock cycles (reset value on
reset_n
)
Table 148: Dynamic Memory Data-in Active Command Time register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
DAL