Digi NS9750 - Manual (Page 294)

I n t e r r u p t c o n t r o l l e r
2 7 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Vectored interrupt controller (VIC) flow
A vectored interrupt controller allows a reasonable interrupt latency for IRQ-line
interrupts. When an interrupt occurs, the CPU processor determines whether the
interrupt is from a FIQ or IRQ line. If the interrupt comes from the FIQ vector, the
interrupt service routine can be executed without knowing the interrupt source.
If the interrupt comes from the IRQ vector, the CPU performs these steps:
1
Reads the service routine address from the VIC’s ISRADDR register. The read
updates the VIC’s priority hardware to prevent current or any lower priority
interrupts from interrupting until the higher priority interrupt has occurred.
2
Branches to the interrupt service routine and stacks the workspace so the IRQ
can be enabled.
3
Executes the interrupt service routine.
4
Clears the current interrupt from the source.
5
Disables the IRQ and restores the workplace.
6
Writes to the ISRADDR register to clear the current interrupt path in the VIC’s
priority hardware. Any value can be written.
7
Returns from the interrupt service routine.
26 Timer Interrupt 12 and 13
27 Timer Interrupt 14 and 15
28 External Interrupt 0
29 External Interrupt 1
30 External Interrupt 2
31 External Interrupt 3
Interrupt ID Interrupt source