Digi NS9750 - Manual (Page 613)

w w w . d i g i e m b e d d e d . c o m 5 8 9
L C D C o n t r o l l e r
Register bit assignment
LCDINTRENABLE
Address: A080 0018
LCDINTRENABLE is the interrupt enable register. Setting bits within this register
enables the corresponding raw interrupt LCDStatus bits to cause an interrupt to the
system.
Bits Access Mnemonic Reset Description
D31:02 R/W LCDLPBASE 0x00000000 LCD lower panel base address
Starting address of the lower panel frame data in
memory; the address is word-aligned.
D01:00 R/W Not used 0x0 Read as 0.
Table 356: LCDLPBASE register
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
Reserved
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
LCDLPBASE
LCDLPBASE
MBERR
INTR
ENB
VCOMP
INTR
ENB
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
Reserved
Reserved Not used
LNBU
INTR
ENB