Digi NS9750 - Manual (Page 391)

w w w . d i g i e m b e d d e d . c o m 3 6 7
E t h e r n e t C o m m u n i c a t i o n M o d u l e
HT1 stores enables for the lower 32 CRC addresses; HT2 stores enables for the upper
32 CRC addresses.
HT1
Address: A060 0504
Register bit assignment
HT2
Address: A060 0508
Register bit assignment
Bits Access Mnemonic Reset Description
D31:00 R/W HT1 0x00000000 CRC 31:00
Table 226: Hash Table Register 1
Bits Access Mnemonic Reset Description
D31:00 R/W HT2 0x00000000 CRC 63:32
Table 227: Hash Table Register 2
HT1
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
HT1
HT2
13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30
HT2