Digi NS9750 - Manual (Page 759)

w w w . d i g i e m b e d d e d . c o m 7 3 5
U S B C o n t r o l l e r M o d u l e
HcInterruptEnable register
Address: 9010 1010
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterrupt Status register (see "HcInterruptStatus register,"
beginning on page 733). The HcInterruptEnable register controls which events
generate a hardware interrupt. When a bit is set in the HcInterruptStatus register
and the corresponding bit in the HcInterruptEnable register is set and the
MasterInterruptEnable bit (D31) in this register), a hardware interrupt is requested on
the host bus.
Writing a 1 to a bit in this register sets the corresponding bit; setting a bit to 0 leaves
the corresponding bit unchanged. On a read, the current value of this register is
returned.
D02 R/W SF 0b StartofFrame
Set by the host controller at each start of a frame and after
the update of HccaFrameNumber. The host controller
generates a SOF token at the same time.
D01 R/W WDH 0b WritebackDoneHead
Set immediately after the host controller has written
HcDoneHead (see "HcDoneHead register," beginning on
page 746) to HccaDoneHead. The host controller driver
should clear this bit only after it has saved the content of
HccaDoneHead.
D00 R/W SO 0b SchedulingOverrun
Set when the USB schedule for the current frame overruns
and after the update of HccaFrameNumber. A scheduling
overrun also causes the SchedulingOverrunCount in the
HcCommandStatus register (see "HcCommandStatus
register," beginning on page 730) to be incremented.
Bits Access Mnemonic Reset Description
Table 426: HcInterruptStatus register