Digi NS9750 - Manual (Page 699)

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Figure 100: ECP reverse channel transfer cycles
Data and command FIFOs
Separate data and command FIFOs are provided in the forward direction, and a single
FIFO is provided in the reverse direction.
These FIFOs can be accessed either through the appropriate DMA channel (see
Table 310: "DMA channel assignments" on page 509) or directly by the CPU using
access registers provided in this 1284 interface.
Reading or writing these direct access FIFO registers with DMA control
selected results in a bus error.
Direct access registers, as well as all 1284 registers, use little endian byte
ordering, where byte 3 [31:24] is the most significant byte and byte 0 [7:0]
is the least significant byte. Before accessing these registers through the
CPU, however, you must first indicate the endianness of the AHB to the 1284
peripheral. Do this using the Endian Configuration register in the BBus
utility.
For normal operation, it is recommended that you configure this 1284
interface for DMA control. DMA provides a faster and more efficient
interface between IEEE 1284 and the rest of the NS9750. CPU mode is more
suitable for diagnostic and testing purposes.
The forward command FIFO is provided solely for the user’s benefit, to pass any
user-defined, non-IEEE 1284 compliant commands from the host to the NS9750.