Digi NS9750 - Manual (Page 316)

S y s t e m c o n f i g u r a t i o n r e g i s t e r s
2 9 2 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Register bit assignment
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
D07 R/W SWWE 0x0 Software watchdog enable
0 Software watchdog disabled
1 Software watchdog enabled. Once this is set, it cannot
be cleared.
D06 N/A Reserved N/A N/A
D05 R/W SWWI 0x0 Software watchdog interrupt clear
Write a 1, then a 0 to this bit to clear the software
watchdog interrupt.
D04 R/W SWWIC 0x0 Software watchdog interrupt response
0 Generate an interrupt
1 Generate the reset
D03 N/A Reserved N/A N/A
D02:00 R/W SWTCS 0x0 Software watchdog timer clock select
000 CPU clock / 2
001 CPU clock / 4
010 CPU clock / 8
011 CPU clock / 16
100 CPU clock / 32
101 CPU clock / 64
110 Reserved
111 Reserved
Table 183: Software Watchdog Configuration register