Digi NS9750 - Manual (Page 104)

M e m o r y M a n a g e m e n t U n i t ( M M U )
8 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Access is permitted and an off-chip access is not required — the cache
services the access.
Access is not permitted — the MMU signals the CPU core to abort.
If the TLB misses (it does not contain an entry for the MVA), the translation table walk
hardware is invoked to retrieve the translation information from a translation table in
physical memory. When retrieved, the translation information is written into the TLB,
possible overwriting an existing value.
At reset, the MMU is turned off, no address mapping occurs, and all regions are
marked as noncachable and nonbufferable.
MMU program accessible registers
Table 31 shows the CP15 registers that are used in conjunction with page table
descriptors stored in memory to determine MMU operation.
Register Bits Description
R1: Control register M, A, S, R Contains bits to enable the MMU (M bit), enable data address
alignment checks (A bit), and to control the access protection
scheme (S bit and R bit).
R2: Translation Table Base
register [31:14] Holds the physical address of the base of the translation table
maintained in main memory. This base address must be on a 16
KB boundary.
R3: Domain Access Control
register [31:0] Comprises 16 two-bit fields. Each field defines the access
control attributes for one of 16 domains (D15 to D00).
R5: Fault Status registers,
IFSR and DFSR [7:0] Indicates the cause of a data or prefetch abort, and the domain
number of the aborted access when an abort occurs. Bits [7:4]
specify which of the 16 domains (D15 to D00) was being
accessed when a fault occurred. Bits [3:0] indicate the type of
access being attempted. The value of all other bits is
UNPREDICTABLE. The encoding of these bits is shown in
Table 32, “Priority encoding of fault status,” on page 85).
R6: Fault Address register [31:0] Holds the MVA associated with the access that caused the data
abort. See Table 32, “Priority encoding of fault status,” on
page 85 for details of the address stored for each type of fault.
Table 31: MMU program-accessible CP15 registers