Digi NS9750 - Manual (Page 364)

E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 4 0 N S 9 7 5 0 H a r d w a r e R e f e r e n c e
D28 R/W ERXSHT 0 Accept short (<64) receive frames
0 Do not accept short frames
1 Accept short frames
When set, allows frames that are smaller than 64 bytes to
be accepted by the
RX_WR logic.
ERXSHT is typically set for debugging only.
D27:24 R/W Not used 0 Always write as 0.
D23 R/W ETX 0 Enable TX packet processing (see "Transmit packet
processor" on page 327)
0 Reset TX
1 Enable TX
Used as a soft reset for the TX. When cleared resets all
logic in the TX and flushes the FIFOs.
ETX must be set active high to allow data to be sent to the
MAC and to allow processor access to the TX buffer
descriptor RAM.
D22 R/W ETXDMA 0 Enable transmit DMA
0 Disable transmit DMA data request (use to stall
transmitter)
1 Enable transmit DMA data request
Must be set active high to allow the transmit packet
processor to issue transmit data requests to the AHB
interface.
Set this bit to 0 to temporarily stall frame transmission,
which always stalls at the completion of the current frame.
The 8-bit address of the next buffer descriptor to be read
in the TX buffer descriptor RAM is loaded into the
TXSPTR register when the transmit process ends.
If the transmit packet processor already is stalled and
waiting for TCLER (see "TCLER" on page 343),clearing
ETXDMA will not take effect until TCLER has been
toggled.
This bit generally should be set after the Ethernet transmit
parameters (for example, buffer pointer descriptor) are
programmed into the transmit packet processor.
D21 R/W Not used 1 Always write as 1.
D20 R/W Not used 0 Always write as 0.
Bits Access Mnemonic Reset Description
Table 206: Ethernet General Control Register #1