Mii management command register, Clocks field settings, Register bit assignment – Digi NS9750 User Manual
Page 384
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E t h e r n e t C o n t r o l a n d S t a t u s r e g i s t e r s
3 6 0
N S 9 7 5 0 H a r d w a r e R e f e r e n c e
Clocks field settings
MII Management Command register
Address: A060 0424
Register bit assignment
Note:
If both SCAN and READ are set, SCAN takes precedence.
CLKS field
Divisor
AHB bus clock for 2.5 MHz
AHB bus clock for 12.5 MHz
000
4
50 MHz
001
4
50 MHz
010
6
75 MHz
011
8
100 MHz
100
10
101
20
50 MHz
110
30
75 MHz
111
40
100 MHz
Bits
Access
Mnemonic
Reset
Description
D31:02
N/A
Reserved
N/A
N/A
Table 219: MII Management Command register
Reserved
READ
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
SCAN
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