Digi NS9750 - Manual (Page 874)

I n d e x - 4
Carry Register 2 Mask register 382
Centronics mode. See compatibility
mode.</Emphasis>
chip select 1 memory configuration 119
CLD signal 42
Clock Configuration register 293
clock frequency settings
13
clock generation/system pins 26
clock generator 7
clock timing 837 - 839
clocks, LCD 565
coarse page tables 84 , 87 , 90 , 92
Collision Window/Retry register
355
combined transmit and receive statistics
counters 368
Command Transmit Data register 548
compatibility mode 671
data transfer cycle
671
Configuration Address Data Port
register 411
Configuration Address Port register 411
Configuration register 552
Configuration register, memory
207
configuring the NS9750 for CardBus
support 463
context (static) RAM 502
control in packets 711
control logic, BBus bridge
469
,
472
-
473
Control register, memory
205
conventions, documentation xxi
Core Phase (IEEE 1284) register 704
CPU 47 - 114
about the ARM926EJ-S processor 48
accessing the CP15 registers
52
caches and write buffer 105 - 111
core 47
DSP 78
Jazelle (Java) 77
MMU 78 - 105
access permissions and domains
79
address translation
81
-
95
coarse page table descriptor 87
disabling 104
enabling 103
external aborts 102
fault checking sequence
99
features 78
fine page table descriptor 88
first-level descriptor 84
first-level fetch 84
MMU faults and aborts
95
-
98
program accessible registers
80
second-level descriptor 89
section descriptor 86
subpages 95
TLB structure 104
translated entries 79
translating parge page
references 91
translating section references 89
translating small page
references
93
translating tiny page
references 94
translation table base 82
noncacheable instruction fetches 111
R0, ID code and cache type status
registers 55 - 57
R1, Control register 58 - 60
R10, TLB Lockdown register 73
R11 register 74
R12 register
74
R13, Process ID register 75 - 77
R14 register 77
R15, Test and debug register 77
R2, Translation Table Base register 61